CARIOCA Final Prototype Info Page

Francis Anghinolfi¹, Walter Bonivento^1,2, Pierre Jarron¹, Anatoli  Kachtchouk^1,3, Danielle Moraes¹, Nicolas Pelloux^1,4, Werner Riegler¹, Delia Rodriguez¹, Burkhard Schmidt¹ , Filipe Vinci Dos Santos¹

¹ CERN, ² now at INFN Cagliari, ³ now at INFN, ⁴ now at STMicroelectronics 

CARIOCA is an 8channel Amplifier-Shaper-BaselineRestorer-Discriminator Frontend Chip fabricated in in IBM 0.25um CMOS for the Multi Wire Proportional Chambers of the LHCB muon system. Typical specification numbers are peaking time of <15ns for detector capacitance up to 220pF, ENC of less than approx. 2000+40e-/pF, input resistance of <50 Ohm, Unipolar Signal Shaping, LVDS output, fast baseline recovery for signals exceeding the linear range.

The final prototype arrived September 15th and is currently being tested. The engineering run is scheduled for 2004.

This page is intended for internal LHCb-Muon use only and should allow the users of CARIOCA to get an overview of all the CARIOCA characteristics. During the test and evaluation period, that should be concluded by the end of the year (2003), the page will be used like an online logbook and will continuously be filled with new results.

Questions and Comments to werner.riegler@cern.ch are very welcome, since the page should in the end convert into a complete user's manual for the chip.

The chip is subject of a doctoral thesis by danielle.moraes@cern.ch and a diploma thesis by delia.rodriguez@cern.ch 

The most recent overview can be found in the documents of the comprehensive review in February 2003. A description of the final prototype can be found here.

CARIOCA10 measurements:

• Sensitivity
• Noise
• Offsets
• Analog shapes
• Chamber Tests
• Power consumption
• Input protection tests
• Test board details
• Tools and gadgets for testing
• Radiation tests
• Overvoltage test
• Internal test pulses
• Source Count Rates
• Wafer Details